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Resource Efficient Encryption IP Cores
The Advanced Encryption Standard (AES), standardized by NIST in 2001 and approved by NSA for classified data, is at the heart of almost all modern data security protocols. With approaching 100 design-ins across a range of target FPGA technologies, Algotronix' Advanced Encryption Standard IP cores offer a well proven and competitively priced solution. Algotronix AES cores have been selected by many of the largest defense electronics companies and have been deployed by four NATO countries.
Unlike our high performance products the resource efficient AES cores are not pipelined or parallelised and support internal data path widths smaller than the 128 bit AES block size. Depending on configuration and target FPGA chip data throughput ranges from tens of megabits per second to low gigabits per second.
As well as AES we now offer an IP core for the GOST (Kuznyechik) cipher an AES-like cipher standardised in Russia. While AES is definitely the preferred option at this time designing a product with the flexibility to use either the AES or GOST cipher can expand its geographical market and provide a fallback option for customers should the security of AES ever be called into question.
The encryption cores are supplied as a complete package of VHDL or Verilog source code. The IP cores can be targeted at FPGAs from Xilinx, Intel (formerly Altera), Microsemi and Lattice. Source code reduces the cost and complexity of a security audit. It allows customers to confirm that no virus or Trojan code is incorporated and that it cannot be forced into unauthorised states or operations. This can significantly reduce the cost and time to conduct a security audit. Demonstration designs are available which show the cores working on low cost vendor evaluation boards.
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