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AES Keywrap Core
AES Keywrap Core
 
Price: $12,000.00



Product Code: AES-KEYWRAP


Target Technology*: 		Xilinx
Intel (Altera)
Microsemi
Platinum - All FPGA Vendors [Add $2,000.00]
Lattice

Implementation Language*: 		Both VHDL and Verilog (option available for multi-project licenses only) [Add $2,000.00]
Verilog
VHDL
Description Ordering Information
 
This core extends the Algotronix G3 Advanced Encryption Standard (AES) core by providing a secure, standardized method for loading cryptographic keys into the encryption unit. The AES-G3 core is included within this product.
The AES Keywrap algorithm was developed by National Institute of Standards and Technology (NIST) and was adopted by the Internet Engineering Task Force (IETF) as RFC 3394. Use of the AES Keywrap algorithm is also specified in the W3C XML Security Specification and in the IEEE draft standard for encryption of data on hard disks (IEEE P1619). In order to meet specifications such as FIPS140-2 level 2 and higher or the equivalent Common Criteria Protection Profiles protection must be provided for Critical Security Parameters (CSPs) such as cryptographic keys entering the encryption unit. The Key-Wrap algorithm provides an approved mechanism for cryptographically protecting CSPs as they enter the security module.

Datasheets and Applications Information:
Features
  • Provides a secure method of transferring keys into the Algotronix AES G3 core
  • Implements IETF RFC 3394 and the NIST AES Keywrap specification specified as an Approved Key Establishment Technique in FIPS 140-2
  • Supports 128, 192 and 256 bit keys
  • Compile as Wrap, Unwrap or Wrap/Unwrap
  • Supplied as portable VHDL to allow customers to conduct their own code review in high-security applications
  • Supplied with test bench implementing all vectors from the IETF and NIST specification.


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